Parallel GPS signal acquisition and tracking design and analysis using an FPGA

Abstract

The purpose of this research is to design and model a digital system to acquire, lock, and track a GPS signal in parallel on an FPGA. This project aims to reduce the receiver's time to first fix from a cold start. Applications for this research include high precision targets requiring worldwide coverage where a stored almanac is not acceptable and a fast time to first fix is needed. It can also be utilized in aviation and safety of life applications where it is imperative that faulty data is immediately known and excluded. The uniqueness of this project allows ultra-low energy applications with only volatile memory and sleep currents in the æA range. Computer simulations have been performed for: (1) replicating GPS satellite C/A code, (2) determining which satellites are visible, (3) coding a hardware description of parallel correlation, locking, and tracking. The system will be distinctive for applications where there is no need or possibility for storage of almanac information to obtain time to first fix (TTFF) with high speed. During these trials an 'out of the box' cold start scenario is performed each time the code is run. The results have shown that successful GPS signal acquisition and decoding time is 1.7 seconds using hardware coding and an FPGA.