Left shifting accumulator systems with applications in digital signal processing

Abstract

An algorithm is developed which performs the serial accumulation of parallel input data, while shifting each partial sum to the left. The algorithm is demonstrated to be applicable to the operation of multiplication, and evidence to support its applicability to division is presented. Various configurations of modular elements, including two types of configurations which support fully systolic communication patterns, are presented as suggested modes of algorithm implementation. These systems operate as on-line digital signal processors in which data is processed in the most significant digit first serial fashion, so as to support the chaining of operations such as floating-point multiplication and division. Examples of the operation of the algorithm and its applications to multiplication are presented, based on computer simulation data. Comparative data is presented which supports the conclusion that this system operates with a throughput rate a significant factor higher than existing on-line systems, while utilizing more simplistic hardware modules.