AN ADVANCED LARGE-SIGNAL OPERATIONAL AMPLIFIER MACROMODEL 
FOR WATAND COMPUTER SIMULATION 
BY 
BOWEI RAY HSU 
Submitted in Partial Fulfillment of the Requirements 
for the Degree of 
Master of Science 
in the 
Electrical Engineering 
Program 
re- 4- 14P7 
- 
Advisor I Date 
J I* b1JQi.1,,k , '2 /? 67 
Dean of the Graduate 6~xLol Date 
YOUNGSTOWN STATE UNIVERSITY 
OCTOBER, 1987 
ABSTRACT 
AN ADVANCED LARGE-SIGNAL OPERATIONAL AMPLIFIER MACROMODEL 
FOR WATAND COMPUTER SIMULATION 
BOWEI RAY HSU 
Master of Science, Electrical Engineering 
Youngstown State University, 1987 
A general-purpose large-signal macromodel of an 
operational amplifier is presented. The model simulates the 
following characteristics: input impedance, voltage and 
current offsets, input bias current, gain versus frequency, 
slew rate limiting, output voltage and current limiting, and 
output impedance. The parameters used in the model can be 
taken from a typical data sheet and the user's circuit. 
The model is designed to meet the requirements of 
flexibility, maximum speed, and minimum storage with the 
WATAND package. The macromodel is accurate for general 
purpose large- and small-signal applications. Comparisons 
of model performance with data obtained experimentally are 
presented. 
The capabilities of the model are demonstrated with 
five examples. An inverting amplifier example shows gain 
versus frequency and large-signal input response. The slew 
rate characteristic and output voltage limiting are shown 
with a monostable multivibrator. A single supply non- 
inverting amplifier is tested. The fourth example is a 
triangular wave generator which consists of a comparator and 
an integrator. The last example is a band-pass R-active 
filter. The frequency response of this model is tested. - 
iii 
ACKNOWLEDGEMENTS 
I would like to express my deep appreciation to my 
thesis advisor, Dr. Philip Munro, for his guidance and help 
in this thesis. I would also like to thank Dr. Jane Kestner 
-- 
in the department of psychology who carefully corrected my 
writing. Many thanks to my wife, May, for her support. 
TABLE OF CONTENTS 
.............. ABSTRACT 
ACKNOWLEDGEMENTS .......... 
TABLE OF CONTENTS .......... 
LIST OF FIGURES ........... 
LIST OF TABLES ........... 
CHAPTER 
........ I. INTRODUCTION 
1.1 OBJECTIVE ....... 
1.2 WATAND PACKAGE ..... 
1.3 MACROMODEL REVIEW ... 
1.4 OVERVIEW ........ 
.... 11. OPERATIONAL AMPLIFIER 
...... 2.1 INTRODUCTION 
...... 2.2 INPUT STAGE 
2.2.1 INPUT OFFSET VOLTAGE 
2.2.2 INPUT BIAS CURRENT . 
2.2.3 INPUT IMPEDANCE . . 
2.3 INTERSTAGE ....... 
2.3.1 GAIN CHARACTERISTICS 
2.3.2 SLEW RATE ..... 
.... 2.3.3 COMMON-MODE REJECTION RATIO 
2.4 OUTPUT STAGE .............. 
.......... 2.4.1 OUTPUT IMPEDANCE 
........ 2.4.2 OUTPUT VOLTAGE SWING 
.... 2.4.3 OUTPUT SHORT-CIRCUIT CURRENT 
PAGE 
ii 
iii 
iv 
vi 
viii 
....... 2.5 FET OPERATIONAL AMPLIFIER 
I11 . DEVELOPING THE OP AMP MACROMODEL ...... 
3.1 INTRODUCTION .............. 
3.2 INPUTSTAGE ............. 
3.3 INTERSTAGE ............... 
3.4 OUTPUT STAGE .............. 
3.5 THE COMPLETE OP AMP MACROMODEL ..... 
IV . THE WATAND OP AMP MACROMODEL ........ 
............... 4.1OVERVIEW. 
4.2WBLOCKFILE .............. 
4.3 FORTRAN SUBROUTINE ........... 
V . MACROMODEL PERFORMANCE ........... 
5.1 INVERTING AMPLIFIER .......... 
5.2 MONOSTABLE MULTIVIBRATOR ........ 
5.3 SINGLE POWER SUPPLY NON-INVERTING 
AMPLIFIER .............. 
5.4 TRIANGULAR WAVE GENERATOR ....... 
5.5 R-ACTIVE BANDPASS FILTER ........ 
5.6 MODEL COMPARISON ............ 
VI . CONCLUSION ................. 
. . 
...................... REFERENCES 
LIST OF FIGURES 
FIGURE PAGE 
2-1 Block Diagram of a Basic Op Amp ........ 6 
.............. 2-2 Bode Plot for Op Amp 9 
2-3 Effect of Slew Rate on Voltage Follower Output . 11 
3-1 Function Blocks of a Basic Op Amp ....... 15 
3-2 Boylels Op Amp Input Stage Model ........ 16 
Glesner
l
s Op Amp Input Stage Model ....... 17 
Sanchez-Sinencio
l
s Op Amp Input Stage Model . . 17 
Weil and McNamee
l
s Op Amp Input Stage Model . . 19 
Proposed Op Amp Input Stage Model ....... 19 
The Simpler Op Amp Input Stage Model ...... 21 
Vlachls Intersatge Model ............ 22 
The Q Source Method Interstage Model ...... 24 
The Output Stage Model ............ 22 
The RC Circuit Method Op Amp Macromodel .. 28 
..... The Q Source Method Op Amp Macromodel 28 
A Noninverting Amplifier ............ 30 
The Output Voltage V2 of the Interstage for 
Large Vi ................... 30 
. . 
.... The Output Voltage of the Modified Model 3-1 
OpAmpMacromodels ............... 34 
An Inverting Amplifier Circuit and its WATAND 
Netlist ................... 50 
WATAND and Experimental Voltage Gain Versus 
Frequency .................. 51 
. 
Voltage Limiting Effect with V.S = 0.3 V 
Amplitude .................. 51 
vii 
5-4 Voltage Limiting Effect with V.S = 10 V 
.................. 
Amplitude 53 
5-5 A Monostable Multivibrator Circuit and its WATAND 
................... 
Netlist 54 
5-6 The Input/Output Voltages of the Monostable 
-- 
............... Multivibrator. 56 
5-7 A Single Power Supply Noninverting Amplifier 
Circuit and its WATAND Netlist ......-. 57 
5-8 Output Waveform of the Single-Supply Amplifier . 58 
5-9 Voltage Gain as a Function of Frequency .... 58 
5-10 A Triangular Wave Generator Circuit and its 
............... WATANDNetlist. 60 
5-11 The DC Initial Point and the Output of the 
Triangular Wave Generator ......... 61 
5-12 An R-Active Bandpass Filter Circuit and its 
............... WATANDNetlist. 62 
5-13 The Response of an R-Active Bandpass Filter . . 63 
LIST OF TABLES 
TABLE PAGE 
4-1 RC circuit Method of Op Amp WBLOCK File .... 35 
4-2 Q Source Method of Op Amp WBLOCK File ..... 37 
4-3 Macromodel Parameters ............. 38 
4-4 LF355 WBLOCK File ............... 39 
4-5 RC Circuit Method Fortran Subroutine ..... 41 
4-6 Q Source Method Fortran Subroutine ...... 45 
5-1 DC Solutions of the Inverting Amplifier .... 52 
5-2 DC Solutions of the Monostable Multivibrator . 55 
5-3 Simulation Time Comparison .......... 64 
CHAPTER I 
INTRODUCTION 
1.1 OBJECTIVE 
Computer-aided design (CAD) has become an important 
tool for circuit analysis and design. With CAD simulation 
programs, engineers can simulate a circuit, change the 
components, alter elements
1 
values, vary parameters, and 
observe the change at any point in the circuit. Circuit 
simulation has largely replaced "breadboarding
1
' in circuit 
analysis and design. 
The integrated circuit operational amplifier (op amp) 
is very popular and widely used in electronic circuits. 
When a circuit is designed containing op amps, the 
characteristics of op amps are frequently assumed to be 
ideal, i.e., gain and input impedance are infinite and 
- 
output impedance is zero. In many cases, this assumption is 
not adequate. For example, in large-signal response, the 
output voltage is limited by the slew rate, the maximum - 
change rate in the output. The present built-in op amp in 
WATAND [I] is a linear element which has ideal op amp 
characteristics. An existing user-defined op amp model for 
WATAND [2] also is not adequate for large-signal response. 
An improved model is necessary when analyzing some circuits- 
containing op amps. 
1.2 THE WATAND SOFTWARE PACKAGE 
WATAND (WATerloo ANalysis and Design), developed at 
the Electrical Department of the University of Waterloo 
[1,3], is an interactive, user-oriented system for 
simulating linear and non-linear electronic circuits. 
WATAND has a large number of built-in linear and non-linear 
elements, such as resistors, capacitors, inductors, diodes, 
transistors, the linear op amp, etc. Besides these built-in 
elements, user-defined elements and subcircuits can be 
defined and used (see Refs. [1,2,4] for examples). The 
WATAND package uses piecewise linear (PWL) methods to 
represent nonlinear characteristics. This method allows a 
user to define the tradeoff between execution time and 
accuracy [5]. This package was designed to meet the 
requirement of maximum flexibility, minimum storage, and 
maximum speed. The WATAND version used in this thesis is 
version 1.10-00. 
- 
1.3 MACROMODEL REVIEW 
Several op amp macromodels have been published. 
Boyle, et a1.- [6] use a simplification technique to-describe 
the input characteristics by using simple ideal elements to 
replace numerous real elements. The other characteristics 
are modeled by a llbuild-upn technique. In this technique, a 
circuit is proposed to meet certain external circuit 
- 
specifications without necessarily resembling the original 
circuitry. This macromodel models the input and output 
characteristics, differential- and common-mode gain versus 
frequency characteristics, offset characteristics, and 
large-signal characteristics. 
Glesner and Weisang [7] present a macromodel obtained 
by using the Itbuild-upw technique. This model contains only 
linear elements and uses RC circuits to simulate the 
frequency related characteristics of the op amp. Besides 
those characteristics contained in Boylets model, the 
thermal behavior is also considered in this macromodel. 
Sanchez-Sinencio and Majewski [8] use the wbuild-upn 
technique in their macromodel. The model is developed for 
frequency domain applications and not for nonlinear 
transient operation. The large-signal response in frequency 
domain analysis can be simulated in this model. It has many 
mathematical and frequency dependent equations which can not 
be used directly in WATAND. 
Weil and McNamee [9] use 13 diodes to model the - 
nonlinear characteristics of op amp. The ubuild-upll 
technique is used in this model. Those op amp characteris- 
tics contained in Boylels model can be simulated in this 
- - 
model. 
1.4 OVERVIEW 
The following chapters develop a general macromodel 
for an integrated circuit operational amplifier. Chapter I1 
- 
briefly describes the op amp's functional blocks and 
properties which are used in the macromodel. The step by 
step development of the op amp macromodel is contained in 
Chapter 111. Chapter IV describes the method for using 
#DEfine and a user written Fortran subroutine to build the 
op amp macromodel into WATAND. Five examples of the 
application of the op amp macromodel are contained in 
Chapter V. These examples are used to test the op amp 
macromodel's function and are compared to experiment. 
CHAPTER I1 
OPERATIONAL AMPLIFIER 
2.1 INTRODUCTION 
For the design of the operational amplifier (op amp) 
macromodel, the op amp's characteristics - input impedance, 
input offset voltage, open-loop voltage gain, etc. - are 
considered, therefore these op amp characteristics are 
discussed in this chapter. The op amp is a direct-coupled 
high-gain amplifier. It amplifies the difference of the two 
input voltages and can be ideally characterized by the 
function 
where Aol is the open-loop gain of op amp and V and V2 
1 
are input voltages. A block diagram of a basic op amp is - 
usually as shown in Fig. 2-1 [lo]. The differential ampli- 
fier in the input stage transfers the differential input - 
voltages to differential currents. These differential 
currents, 
Icl 
and Ic2, are then converted to a single-ended 
current, Iout, in the current mirror block. The inferstage 
changes this current back into voltage, Vtout. The internal 
capacitor, 
Cc 
is used to keep the op amp stable. The out- 
put stage contains unity-gain emitter followers. This stage 
amplifies the output current and provides low impedance 
drive to the load. The properties of the op amp are 
- 
described in the following sections. 
INPUT STAGE INTERSTAGE OUTPUT STAGE 
Icl 
Fig. 2-1 Block Diagram of a Basic Op Amp. 
I I 
IC2 
2.2 INPUT STAGE 
2.2.1 INPUT OFFSET VOLTAGE 
For an ideal op amp with finite gain, the output 
voltage is an amplified replica of the difference between 
two input voltages. The output voltage will be zero when- 
the input voltages are the same. Real op amps do not 
provide this idealized performance because of the imbalance 
of the internal circuit and the common-mode gain coupled 
with very high gain. The input offset voltage, Vos, is the 
- 
amount of the input voltage added between two input 
terminals to make the output voltage zero. For the 741 op 
w u 
aJRRENTMIRRoR 
. 
I - 
Iout 
UNITY-GAIN ETclTER 
FOm 
IllmmmG 
AMPXFIER 
- 
v'out 
amp, Vos is 6 mV maximum. With the help of an offset 
voltage compensating network, the output voltage can be 
reduced to zero. 
2.2.2 INPUT BIAS CURRENT 
Input bias currents, Ibl and Ib2, are the base bias 
currents of the bipolar input transistors or the gate 
leakage currents of JFETs. Ibl and Ib2 are not equal 
because of internal circuit imbalance and non-identical 
input transistors. The difference between Ibl and Ib2 is 
the input offset current, IoS For the 741 op amp, a 
typical value of input bias current, 
Ib, 
is 500 nA at supply 
voltages of f15 V and Ios is 200 nA. 
2.2.3 INPUT IMPEDANCE 
The ideal op amp has an infinite input impedance, Zi. 
A real op amp has a finite input impedance which can be 
represented as a combination of a difference-mode impedance, - 
'idf 
and a common-mode input impedance, Zic. 
Zid and Zic 
are both ac signal impedances, that is 
Rid is generally in the range of lOOk ohms up to lOOM 
ohms for bipolar op amps or 1012 ohms for FET op amps [lo]. 
- 
The difference-mode input capacitance, Cid, is typically 
2 pF for both types of op amps. The value of Ric is in the 
range of 1M ohms to lOOG ohms. The common-mode input capa- 
citance, Cic, is 3 to 5 pF for FET op amps and 2 to 3 pF for 
bipolar op amp. Zid is increased by the use of feedback but 
Zic remains unaffected [Ill. 
2.3 INTERSTAGE 
2.3.1 GAIN CHARACTERISTICS 
The voltage gain of the op amp is usually provided by 
the input stage and interstage. The differential-mode 
voltage gain, Adm, is the ratio of the voltage change in the 
output to the change in the difference between the two 
inputs. The open-loop voltage gain is essentially identical 
to the differential-mode voltage gain. The open-loop gain 
6 
is usually in the range lo5 to 10 at low frequency [Ill. 
The common-mode voltage gain, 
Acmt 
is the ratio of the 
voltage change in the output to the change of the common- 
mode input. Acm is usually very small compared to Adm. - 
The op amp gain is frequency dependent because of the 
capacitive components in the op amp circuit. There are 
three major sources responsible for capacitive effects [12]: 
- - 
1) the compensation capacitor which is used for stabliza- 
tion, 2) the junction capacitors in the bipolar transistors 
or FETs which compose the op amp, and 3) the stray capaci- 
tance of the semiconductor device's substrate. The cumula- 
tive effect of these capacitive effects causes the gain to - 
decrease as the frequency increases. A typical Bode plot is 
shown in Fig. 2-2. 
The frequency fl is the first break point frequency 
of the op amp and is usually small (around 10Hz). For high- 
gain IC op amps, the second break point frequency, f2, is 
usually very large (1 to 3 MHz) compared to fl [ll]. The 
unity-gain frequency, f is defined as the frequency at 
Uf 
which the gain is unity. The gain as a function of frequen- 
cy can be expressed in the form [lo] 
where fl < f2 < f3 < ... 
Gain (db) 
Fig. 2-2 Bode Plot for Op Amp. 
2.3.2 SLEW RATE 
The slew rate specification of an op amp is the 
maximum rate of change of output voltage with respect to 
time, (dvo/dt) max. Slew rate limitation arises because of 
current limiting of an op amp when a high frequency and 
large (quickly changing) signal is applied. 
For most op amps, the positive going slew rate is 
slightly different from the negative going slew rate [13]. 
The slew rate effect is illustrated in a voltage follower 
with rectangular-pulse input as shown in Fig. 2-3, since 
these represent the worst case condition for slew rate in 
the op amp. For the NPN input stage, the output waveform 
shows a step "enhancementtt on the positive going output and 
a Itdegradationn in the negative going output. For the PNP 
input stage, these effects are reversed as shown by V (t)- 
OP 
in Fig. 2-3. 
- 
2.3.3 COMMON-MODE REJECTION RATIO 
The common-mode rejection ratio (CMRR) can be defined 
as the ratio of the differential voltage gain, Ad, to the 
common-mode voltage gain, Acm, that is, 
- - 
CMRR = Ad/Acm 
For the ideal op amp, Acm would be zero and therefore CMRR 
ideally would be infinite. The actual op amp has a non-zero 
common-mode voltage gain which is generally less than 1.0 - 
(121. The CMRR is a function of frequency and decreases as 
the frequency is increased. 
INPUT 
OUTPUT FOR 
NPN INPUT 
STAGE 
OUTPUT FOR 
PNP INPUT 
STAGE 
Fig. 2-3 Effect of Slew Rate on Voltage Follower Output. 
2.4 OUTPUT STAGE 
2.4.1 OUTPUT IMPEDANCE 
For the ideal op amp, the output impedance is zero. 
-. The output resistance of the op amp is the equivalent 
resistance that can be measured between the output terminal 
and the ground. For a real op amp, Ro is generally in the 
range of 10 to 100 ohms. With feed back in a circuit using 
an op amp, Ro can be reduced to the milliohm range [Ill. 
2.4.2 OUTPUT VOLTAGE SWING 
The output voltage swing, Vomax, is limited by the 
supply voltages. For the 741 op amp, Vomax is guaranteed to 
be between +13 V and -13 V for R1 > 2K ohms and supply 
voltages of f15 V. 
2.4.3 OUTPUT SHORT-CIRCUIT CURRENT 
Output short-circuit protection is usually provided 
to prevent op amp damage due to momentary shorts to ground- 
or to either of the power supply voltages. For the 741 op 
amp, the short-circuit current, Isc, is 25 mA. 
- - 
2.5 FET OPERATIONAL AMPLIFIER 
The input impedance of op amps using bipolar transis- 
tors is usually in the range of several hundred kilohms to 
megaohms because the base-emitter junction is forward 
biased. For op amps using junction field-effect transistors 
(JFETs) in the input stage, the input terminal is the gate 
which is one side of the reverse-biased gate-channel 
junction. The input resistance is much higher than the 
bipolar op amp's input impedance, with values well up into 
the gigaohm range. The input current of the JFET device is 
the gate current and is the reverse leakage current of the 
gate-channel junction. The current is usually around 10 PA, 
while the base current of bipolar transistor is in the 
microampere range. For op amps using metal-oxide-silicon 
FET (MOSFETs), the gate terminal is separated by a thin 
insulating layer of silicon dioxide. As a result, extremely 
high values of input resistance in the teraohm (1012 ohm) 
range can be obtained. The gate current is also extremely 
small, often below 1 PA. 
The slew rate of an op amp is limited by the 
quiescent current, 
IQ 
[ll]. The input resistance and input 
bias current of the bipolar op amp are both directly 
dependent on the quiescent current I 
Q' 
Thus a high slew 
rate is difficult to obtain. For FET-input op amps the gate 
current is not dependent on the quiescent current. So, a 
relatively large current I can be used in the design, that 
Q 
is a large slew rate (50 to 75 V/ps) and a high unity-gain 
- - 
frequency (-20MHz) can be obtained. 
The advantages of FET op amps over bipolar op amps 
are higher input resistance, lower input bias and offset 
current, higher slew rate, and higher unity-gain frequency. 
The disadvantage is the lower voltage gain because FETs - 
often have 30 to 100 times smaller transfer conductance than 
bipolar transistors [11,13]. 
CHAPTER I11 
DEVELOPING THE OP AMP MACROMODEL 
3.1 INTRODUCTION 
Circuit simulation has proven to be very useful in 
the analysis or design of electronic systems. Most 
electronic circuits contain many integrated circuits (ICs) 
today. If these ICs are modeled at the device level, the 
circuit simulation program will require large memory and 
execution time. The solution to this problem is using 
macromodels which model the terminal behavior to the desired 
degree of accuracy with a comparatively small number of 
circuit elements. The 741 op amp, if modeled at the device 
level, would consist of 96 nonlinear elements and 131 linear 
elements in WATAND. Using the macromodel presented by 
Glesner and Weisang [7], the op amp model would only contain 
eight nonlinear and fourteen linear elements. This 90% 
reduction in model size using the macromodel instead of the 
device level model would result in significantly less 
simulation time and less memory space. 
Two macromodeling procedures have been introduced 
[6]. One is simplifying the circuitry by using simpler 
circuits with ideal elements. The other, the vtbuild-upw 
procedure, simulates the terminal behavior by an equivalent 
circuit without necessarily resembling the original 
circuitry. The macromodel presented in this chapter uses 
the wbuild-uplt technique and is based on the basic diagram 
shown in Fig. 3-1. The following sections discuss the 
development of the op amp macromodel. 
3.2 INPUT STAGE 
The input stage of the op amp macromodel simulates 
the functioning of the real op amp input stage. It models 
the input offset voltage, input bias current, input offset 
current, differential-mode impedence, common-mode impedence, 
differential voltage gain, and common-mode voltage gain. 
The differential gain will be modeled in the interstage for 
simplification. 
Boylets model [6] shown in Fig. 3-2 uses a simplifi- 
cation technique to model the input stage by using a 
differential amplifier and ideal elements. Because in 
WATAND each transistor model (Ebers-Moll model) contains 
four current sources and six passive elements, the circuit- 
INPUT STAGE INTERSTAGE OUTPUT STAGE 
Fig. 3-1 Function Blocks of a Basic Op Amp. 
vi (+I 
> 
vi(-) 
3 
* 
INHR: 
claFacrEFusTIC 
TRANSFER 
claFacrEFumc 
CIR'PUT 
claFamSITc 
CVrPUT 
> 
of this input stage model would contain nine current 
sources, nineteen passive elements, and ten nodes. Since 
this model is big, it would take relatively large memory and 
CPU time. 
Other macromodels [7,8,14] -use the rlbuild-upv 
technique. Glesner
l
s model [7] shown in Fig. 3-3 uses one 
voltage source to represent the input offset voltage and 
three current sources to represent input offset current and 
bias currents. It contains input differential mode 
impedance and common-mode resistance. It also simulates the 
Fig. 3-2 Boylels Op Amp Input Stage Model. 
NIN 
Fig. 3-3 Glesner's Op Amp Input Stage Model. 
Fig. 3-4 Sanchez-Sinencio's Op Amp Input Stage Model. 
frequency dependent common-mode rejection behavior by using 
one dependent voltage source, two resistors and a capacitor. 
The model needs five dependent sources, seven passive 
elements and six nodes. 
The model of Sanchiez-Sinencio and Majewski [8] shown 
in Fig. 3-4 simulates the differential and common-mode input 
impedance. An extra stage (Ic, Rc, and Cc) must be used to 
provide the frequency dependent common-mode rejection ratio, 
CMRR(d), when used in WATAND. The model would need two 
dependent sources, seven passive elements and five nodes. 
The model proposed by Weil and McNamee [9] shown in 
Fig. 3-5 uses two diodes and a current source to model the 
impedance, input offset current, and nonlinear input bias 
current. It needs four dependent sources, six passive 
elements, and seven nodes when modeled in WATAND. 
The proposed model shown in Fig. 3-6 is based on 
Glesner's model but with some modification. Ri and Ci make 
up the input differential impedance. Ric is the input 
common-mode resistance. Vos is the input offset voltage. 
The sign for Vos may be positive or negative. 
Ibl and Ib2 
are input bias currents in terms of average bias current, 
Ib, and offset current, 
Ios' 
and 
IOS 
may be positive or negative. The signs of Ibl and Ib2 
Fig. 3-5 Weil and McNamee8s Op Amp Input Stage Model. 
+ 
'i 
- 
NON, - N - I 
Fig. 3-6 Proposed Op Amp Input Stage Model. 
INV 
-+ 
ry 
'0s Dil Di2 
Ii 
- 
Rc,2 
shown in Fig. 3-6 are positive for NPN-input or FET/bipolar 
op amps where the bias currents enter the op amp. For PNP- 
input op amps, these signs are reversed. Because the values 
Of VOSt IOS, and Ib are random, one may want to use the 
Monte-Carlo analysis (see Ref. [15]) to model the random 
effect of these parameterst values. 
The voltage source Vm is used for the voltage level 
between the input stage and the output stage. For a 
balanced supply voltage situation, the middle point (common 
point), VA, should be zero voltage (ground), but for an 
unbalance supply voltage case, the middle point is not at 
zero voltage. The voltage level is 
R and Cc (see Fig. 3-6) are used for the 
Icm, c 
frequency dependent CMRR. 
- 
where fcmrr is the breakpoint frequency of CMRR obtained 
from the manufacturer's specifications. 
Fig. 3-7 The Simpler Op Amp Input Stage Model. 
The model has five dependent sources and six passive 
elements. Since the CMRR is usually very large, the common- 
mode gain is very small compared to differential gain. The 
CMRR stage is, therefore, omitted for simplicity. The final 
simplified input stage model is shown in Fig. 3-7. Two 
voltage sources, two current sources, four passive elements, 
and five nodes are used in this model. - - 
3.3 INTERSTAGE 
The interstage models the gain which is affected by 
frequency and slew rate. Most interstage models use the 
Itbuild-upn technique [6-91. The models use the frequency - 
domain method (using RC circuits) to simulate the pole 
function. These models provide two-pole (-breakpoint) 
characteristics. Fig. 3-8 shows Vlach's model [14] for the 
R and C2 provide the first pole and slew interstage. 12, 
rate characteristics. The slew rate is modeled by limiting 
where Im = the maximum output current swing 
Vomax 
= the maximum output voltage swing 
Ro 
= output resistance 
SR = slew rate 
= the first breakpoint frequency 
Fig. 3-8 Vlachts Interstage Model [14]. 
R1' 5, 
and Il form the second pole characteristic. R1 is 
chosen arbitrarily. 
where w2 = the second break point frequency. 
Another method for modeling the interstage is to use 
the time domain equation to simulate the two-pole function. 
v2 (s) 
Gain = 
- 
vi (s) ( 1+s/lQ1) ( 1+s/u2 1 
Taking the inverse Laplace transform [16], the equation 
becomes 
- - 
Wl+d2 dV2(t) 1 
V2 (t) = A0Vi(t) - - (3.5)- 
1*2 
dt 
%*2 dt
2 
In WATAND a derivative such as dV2/dt can be represented 
with a charge source, Q, or a flux source, F. The Q source 
has a current value equal to dQ/dt, and the F source has 
voltage value equal to dF/dt. Since the F source is 
accompanied with an auxiliary variable in WATAND, employing 
it would make the circuit matrix larger than the model using 
the Q source. Therefore, Eq. 3.5 is modeled by using the 
charge source as shown in Fig. 3-9. 
Therefore as seen from Fig. 3-9, 
Fig. 3-9 The Q Source Method Interstage Model. 
This equation is exactly the same as Eq. 3.5. 
The slew rate characteristic is modeled by limiting 
the current I 
q' 
Eq. 3.6 is given in Ref. [13] 
whereuu = the unity-gain frequency 
SR = the slew rate 
dvo 
SR = - 
The maximum input to the interstage. Vm, is 
=W V 
u m 
Then, the input voltage. Vit is limited as follow: 
dt max 
and 
- 
if Vi < v vi - -vm 
3.4 OUTPUT STAGE 
The output stage simulates the characteristics of 
output impedance, output voltage limit and short-circuit 
current limit. Boyle [6] and Weil [9] use two diodes to 
limit the output voltage. Vlach [14] and Sanchez-Sinencio 
[8] use a nonlinear resistor to limit the voltage. These 
nonlinear elements make the model more complicated to 
simulate on the computer. A simpler method for WATAND is to 
use a voltage source having a voltage limit function. 
where Vo = the output voltage of the op amp 
vomh 
= the maximum output voltage 
Voml 
= the minimum output voltage 
The short-circuit current can be limited by using two 
diodes [6,9], or by using a current source [7]. The latter 
method will be used for the proposed model because it is 
simpler for computer simulation. Fig. 3-10 is the output 
stage for the- proposed model. The equations are -- 
Fig. 3-10 The Output Stage Model. 
where Ro = the output resistance 
'r 
= the voltage across Ro 
I0 
= the output current of the op amp model 
I1 = the current limiter 
Isc = the short-circuit current 
3.5 THE COMPLETE OP AMP MACROMODEL 
- - 
The complete model of the op amp shown in Fig. 3-11 
is the combination of the separated models in Fig. 3-7 to 
3-10. This macromodel uses RC circuits to simulate the 
pole frequencies. Another macromodel shown in Fig. 3-12 
simulates the poles function with Q sources which are part- 
of the #DEFINE element in the WATAND macromodel. The 
difference between these two models is the interstage. The 
Fig. 3-11 The RC Circuit Method Op Amp Macromodel. 
Fig 3-12 The Q Source Method Op Amp Macromodel. 
function for these two macromodels is the same but the 
performance is somewhat different. 
The macromodels shown in Fig. 3-11 and 3-12 work well 
in the small-signal case. However, in a large-signal case, 
because of the large gain in the interstage, that stage's 
output will be very large compared to the power supply 
voltages. Due to the large charge supplied to C1 (see Fig. 
3-11), the output response can not follow the input voltage 
at high frequency. A noninverting amplifier using a test 
macromodel shown in Fig. 3-13 is used to illustrate with 
WATAND . 
Because the slew rate limits the change of 12, V2 
becomes triangular instead of sinusoidal as seen in Fig. 
3-14. When the input voltage of this amplifier goes from 
positive to negative, V2 is very high and C2 takes 
additional time to discharge. The output voltage of this 
amplifier becomes rectangular instead of being a square 
- 
wave. Therefore, the model must be modified to eliminate 
the discharge delay. A voltage reduction in V2 during 
large-signal response must be added. Boylets model [6] 
- - 
provides this voltage limit by using two diodes and a 
dependent variable. 
In this work, V2 is limited by modifying the function 
I2 (dependent source). If V2 exceeds the maximum output 
voltage, I2 is reduced by an amount Id. The equations for - 
Id are 
OP AMP MODEL 
Fig. 3-13 A Noninverting Amplifier. 
7 - 
i,. '41 ,iO-131i 581371315 35-11CT.37 13:::: 13 YSUCMS FILE: NVL 
XT i EIOI.I.IH'JERTINC AMPLIrIER 
vo v2 
I 
! Vo 
! 
- - 
I I 
,QQ1!] 
i 
11 ,OIIOS ,130 1 e ,:II:~ 
i 
;( . 1) 5.13 0 . ;$ i 
T: EXECUTION TIEE: 2,3813 SEC, 
Fig. 3-14 The Output Voltage V2 of the 
Interstage for Large Vi. 
TC V1 ,113.136 tC1381301 01-OCT-87 16134120 YSUCHS FILE: IAIlP 
RT AN IIIUERTINb AMPLIFIER 
Ti EXECUTION TIME: 0,657 ZEC, 
Fig. 3-15 The Output Voltage of the Modified Model. 
Id = exp (V2-Vomh) -1 if V2 > Vomh 
Under this limit, V2 won't go too high above the maximum 
- - 
output voltage. Fig. 3-15 shows the output of the non- 
inverting amplifier using the modified model. 
The Q source model shown in Fig. 3-12 can be modified 
by just changing the dependent current source I that is 
q ' 
W l+WZ dV2 
I = AOVi - 
q dt - [ex~(V~-v~~)-lI 
for V2 
> vomh 
(3.8a) 
for V2 < Voml (3.8b) 
The exponential expressions in Eqs. 3.8a and 3.8b are added 
to limit the voltage in the interstage. 
These op amp models provide for input and output 
characteristics, differential gain versus frequency 
characteristics, offset characteristics, and large signal 
characteristics, such as slew rate, output voltage swing, 
and short-circuit current limiting. Both macromodels are 
capable of working in an unbalanced power supply situation. 
Chapter 4 deals with the implementation of these two 
macromodels in WATAND. 
CHAPTER IV 
THE WATAND OP AMP MACROMODEL 
4.1 OVERVIEW 
To build a model in WATAND, one can use the #DEFINE 
control word to describe the internal circuit and parameters 
of the model. The #DEFINE model may contain a) any WATAND 
linear elements except independent sources, switches and 
mutual inductances, and b) any of four nonlinear elements: 
current source, voltage source, charge source (I=dQ/dt) and 
flux source (V=dF/dt) [4]. A user written Fortran subrou- 
tine is used to evaluate the values of the nonlinear 
characteristics. 
The #DEFINE section of this op amp macromodel is 
stored in a WBLOCK file which is discussed in section 4.2. 
The user written Fortran subroutines are described in 
- 
section 4.3. 
4.2 WBLOCK FILE 
- - 
For convenience, the macromodels developed in Chapter 
3 are redrawn in Fig. 4-1. The WBLOCK file of the op amp 
macromodel using the RC circuit method is shown in Table 4-1 
(see Refs. [4,17] for the detail of WBLOCK Macros). The 
line numbers to the extreme left are not part of the file. 
- 
The default parameter values are for the Fairchild 741 op 
amp. The OA in line 18 is the defined element's name. 
a) Using the RC Circuit Method. 
b) Using the Q Source Method. 
Fig. 4-1 Op Amp Macromodels. 
Table 4-1 RC Circuit Method of Op Amp WBLOCK File. 
OA WBLOCK: 
01 ................................................................. 
02 #* 
03 #* OPERATIONAL AMPLIFIER MODEL USING RC CIRCUIT METHOD 
- 
04 #* WITH 741 DEFAULTS AND ZERO-OFFSET VALUES. 
05 #* 
06 #* IN THE #MODEL SECTION, ENTER 
07 #* 
08 #* OA-MNAME < OA PARAMETERS > 
09 #* 
10 #* IN THE #DATA SECTION, ENTER 
11 #* 
12 #* 0A.MNAME.NAME N1 N2 N3 N4 
13 #* (VI+ VI- VO GND) 
14 #* 
15 #* CREATED 25-OCT-87 B.R. HSU EE DEPT. YSU 
16 ................................................................. 
17 &MODEL 
18 #DE OA 
19 MODEL OA 13 
20 * VSUP 15 -15 A0 2D5 RI 2D6 CI 1.4P RO 75 SR 6.7D5 5D5 
21 * FB 5 3D6 VOS 0 IOS 0 IB 80N RIC 2D9 ISC 25M VOLIM -1.5 2.5 
22 * AUTOSP 1 
23 * SPVI -15 -14 -80M -lM 1M 80M 14 15 
24 * SPVl -15 -14 -80M -lM 1M 80M 14 15 
25 * SPV2 -20 -15 -14 -7 0 7 14 15 20 
26 * SPVR -20 -5 -1.975 -1.875 1.875 1.975 5 20 
27DATA4 15 74 84 93 
28 FUNCTIONS 
29V25 
30Jld 
31J26 
32V64 
33J47 
34J48 
35v94 
36J34 
37 ELEMENTS 
38R15 RI 
39C15 CI 
40 R 1 6 RIC - 
41 R 2 6 RIC 
42R93 RO 
43C74 1M 
44R74 2M 
45C84 3M 
46R84 4M 
47 #M 
48 OA.&MNAME &PARAM 
The OA in line 19 is the Fortran subroutine's name. The 
number 13 after OA is the number of extra storage locations 
reserved for use by the subroutine. Lines 20 to 22 contain 
parameters and their default values. Lines 23 to 26 contain 
sample-point parameter names and their default values. The 
number 4 after DATA in line 27 indicates that the first four 
nodes in the model will be connected to the external 
circuit. The numbers following DATA 4 are the node pairs 
for the independent variables (V15, V74, V84, and V93). 
Lines 28 to 36 make up the FUNCTIONS section. The first two 
numbers following each V and J are the nodes of the 
dependent source. The first four functions, V25, J16, J26, 
and V64, are constant sources which depend only on the 
constant parameters. The linear elements in the op amp 
macromodel are in the ELEMENTS section in lines 37 to 46. 
Values are obtained from parameter values RI, CI, etc., or 
from the extra storage locations for the last four elements. 
- 
Table 4-2 is the WBLOCK file of the op amp macromodel 
using the Q source method. It is similar to Table 4-1 
except that it uses charge sources to simulate the pole 
- - 
frequencies instead of using RC circuits. 
The parameter values of either macromodel can be 
taken from manufacturers
1 
data sheets and from the user
l
s 
circuit. The description of these parameters is given in 
Table 4-3. The default parameter values are for 741 op amp. 
- 
One can use these general WBLOCK files to build other 
op amp models. A WBLOCK file for the LF355, a JFET/bipolar 
Table 4-2 Q Source Method of Op Amp WBLOCK File. 
OA2 WBLOCK: 
.................................................................. 
# * 
#* OPERATIONAL AMPLIFIER MODEL USING Q SOURCE METHOD 
# * WITH 741 DEFAULTS AND ZERO-OFFSET VALUES. 
# * 
#* IN THE #MODEL SECTION, ENTER 
# * 
# * OA2 .MNAME < OA2 PARAMETERS > 
# * 
#* IN THE #DATA SECTION, ENTER 
# * 
# * OA2.MNAME.NAME N1 N2 N3 N4 
# * (VI+ VI- VO GND) 
# * 
#* CREATED 25-OCT-87 B.R. HSU EE DEPT. YSU 
.................................................................. 
&MODEL 
#DE OA2 
MODEL OA2 8 
* VSUP 15 -15 A0 2D5 RI 2D6 CI 1.4P RO 75 SR 6.7D5 5D5 
* FB 5 3D6 VOS 0 IOS 0 IB 80N RIC 2D9 ISC 25M VOLIM -1.5 2.5 
* AUTOSP 1 
* SPVI -30 -15 -10 -1 -8D-2 -7.9D-2 .lo663 .lo763 1 10 15 30 
* SPVl -1D7 -1D5 -1D3 1D3 1D5 1D7 
* SPV2 -30 -15 -14.1 -14 -10 -1 1 10 14 14.1 15 30 
* SPVR -10 -1.975 -1.875 1.875 1.975 10 
DATA4 15 74 84 93 
FUNCTIONS 
v25 
J16 
J26 
V64 
447 
484 
J48 
v94 
534 
ELEMENTS 
R15 RI 
C15 CI 
R16 RIC 
R 2 6 RIC 
R93 RO 
R84 8M 
R74 8M 
#M 
OA2.&MNAME &PARAM 
Table 4-3 Macromodel Parameters. 
PARAMETER DEFAULT UNITS DESCRIPTION 
NAME VALUES 
VSUP Op Amp Supply Voltages 
VSUP .1 15 V Positive supply voltage 
VSUP .2 -15 V Negative supply voltage 
Low frequency open-loop gain 
Input resistance 
Input capacitance 
Output resistance 
Slew rate 
SR. 1 
SR. 2 
Positive going slew rate 
Negative going slew rate 
Break-point frequency 
First break-point frequency 
Second break-point frequency 
FB. 1 
FB. 2 
VOS Input offset voltage 
Input offset current 
Input bias currrnt 
RIC Common-mode input resistance 
ISC Output short circuit current 
- - 
The difference between 
maximum output voltages 
and supply voltages 
VOLIM 
VOLIM. 1 
VOLIM. 2 
Maximum output minus VSUP.l 
Minimum output minus VSUP.2 
AUTOSP Designates automatic sample- 
point selection (=I), 
otherwise, user-specified - 
sample-points are used 
Table 4-4 LF355 WBLOCK File. 
LF355 WBLOCK: 
*************************************t*******************************xa-* 
t* 
#* LF355 OP AMP MODEL 
# * USING THE OA MARC0 WITH LF355 DEFAULTS 
# * 
- 
#* IN THE #MODEL SECTION, ENTER 
# * 
# * LF355.MNAME <LF355 PARAMETERS> 
# * 
#* IN THE #DATA SECTION, ENTER 
# * 
# * LF355.MNAME.NAME N1 N2 N3 N4 
# * (VI+ VI- VO GND) 
# * 
# * CREATED 25-OCT-87 B.R. HSU EEDEPT. YSU 
......................................................................... 
&MODEL 
&PARAM VSUP A0 RI CI RO SR FB VOS IOS IB RIC ISC VOLIM AUTOSP 
* SPVI SPVl SPV2 SPVR 
&DEFAULT VSUP 15 -15 A0 2D5 RI ID12 CI 3P RO 120 SR 5D6 9D6 FB 20 1.5D7 
* VOS 3M IOS 3P IB 30P RIC ID12 ISC 25M VOLIM -2 2 AUTOSP 1 
* SPVI -30 -15 -10 -1 -.l -.01 .01 .1 1 10 15 30 
* SPVl -1D8 -1D6 -1D4 -1D2 1D2 1D4 1D6 ID8 
* SPV2 -50 -15 -14 -10 -1 1 10 14 15 50 
* SPVR -50 -15 -14 -10 -1 1 10 14 15 50 
#M 
OA.&MNAME VSUP &VSUP A0 &A0 RI &RI CI &CI RO &RO SR &SR FB &FB VOS &VOS 
* IOS &IOS IB &IB RIC &RIC ISC &ISC VOLIM &VOLIM AUTOSP &AUTOSP 
* SPVI &SPVI SPVl &SPVl SPV2 &SPV2 SPVR &SPVR 
&DATA 
f D 
CA.&MNAME.&NAME &PARAM 
op amp, is shown in Table 4-4 as an example. The WBLOCK - 
file uses the LF355 parameter values and calls the OA model 
(the RC circuit model). 
- - 
4.3 THE FORTRAN SUBROUTINES 
The user written Fortran subroutines for the RC 
circuit and Q source models are shown in Tables 4-5 and 4-6, 
resp. In this section the RC circuit subroutine is 
described. The Q source subroutine is very similar. - 
In the ICODE=l section, parameters VSUP, VOLIM, ISC, 
and FB are checked. If any invalid value occurs, an error 
message is issued by calling the WATAND utility routine 
USRMSG, and the error flag IERR is set to 1. After all 
parameters are checked, the IERR flag is checked and the 
routine is exited with VAL(1)=1 if IERR=l. Stored 
parameters such as IMH, IML, VM, IB1, etc., are calculated 
and moved to storage positions after the check section. 
If AUTOSP (automatic sample-point flag) is 1, the 
subroutine generates a set of sample-point values by calling 
a WATAND utility routine UDSAP [see Ref. 41. Because the 
input voltage, VI, is limited by IML/GM2 and IMH/GM2 for 
slew-rate limiting in the interstage, sample-point SPVI has 
two break-points, IML/GM2 and IMH/GM2. SA(1) , SA (2) , SA (6) , 
and SA(7) are set at or near the break-points. SA(3) and 
SA(5) are choosen near SA(4) which is 0. SPVl and SPVI 
values are identical for the RC circuit model. 
The maximum and minimum output voltages (VOMH and 
VOML) are used as break-points for SPV2. The supply 
- 
voltages are chosen for SA(1) and SA(7) . SA(2) and SA(6) 
are set equal to VOMH and VOML. VM, a middle point between 
supply voltages, is chosen for SA(4). SA(3) is set between 
- - 
VM and VOML, and SA(4) is set between VM and VOMH. SPVR 
also has two break-points, -ISC*RO and ISC*RO. SA(l), 
SA(2), SA(4), and SA(5) are chosen at or near these break- 
points, and SA(3) is set to 0. 
If the IER return from UDSAP does not equal zero, an 
- 
error message is issued and IERR is set to 1. After all 
sample-points are set, 
IERR is checked again, and if it is 
equal to 1, the routine is exited with VAL(1)=1. 
In the ICODE=2 section, the values of the functions 
(dependent sources) are calculated. The equations used are 
from Chapter 3. 
Table 4-5 RC Circuit Method Fortran Subroutine. 
OA FORTRAN: 
c*********************************************************************** 
SUBROUTINE OA (ICODE,PARtVAR,VALtEPARtMIDAtDERIV) 
c*********************************************************************** 
C 
C OPERATIONAL AMPLIFIER (USING RC CIRCUIT METHOD) 
C 
C CREATED 25-OCT-1987 B.R. HSU EE DEPT. YSU 
........................................................................ 
REAL*8 PAR(1),VAR(1),VAL(1),EPAR(1),DERIV(1,1), 
* SA(7) ,INC(6) ,DE,LEtHE, 
* ERMSG(5) ,CNSA(4), 
* VPOS,VNEGtAO,RItCItRO~SRP~SRNIF1IF2IVOSIIOS~IB~RICtISCt 
* VOLIMH,VOLIML,AUTOSP, 
* C1tR1,C2tR2,GM1,GM2tIMHIIMLIIB1IIB2IVOMHIVOML,VMtLPAR(3l)~ 
* VI,V1tV2,VR,11,12,VLtILtTWOPIIIOIID 
INTEGER ICODE,MIDA(1),IVARtNSA~IER~IERR 
LOGICAL*l ERMSGl(40) ,CNIER(4) 
EQUIVALENCE - 
* (LPAR( I), VPOS ), (LPAR( 2), VNEG ), (LPAR( 3), A0 ), 
* (LPAR( 4) t RI t (LPAR( 5) t CI t (LPAR( 6) r RO 1 t 
* (LPAR( 7) t SRP t (LPAR( 8) t SFUJ (LPAR( 9) t F1 1 t 
* (LPAR(lO), F2 ), (LPAR(ll), VOS ), (LPAR(12), IOS 
* (LPAR(13), IB ) (LPAR(14), RIC ) , (LPAR(15), ISC ) , 
* (LPAR(16), VOLIMH), (LPAR(17), VOLIML), (LPAR(18), AUTOSP) 
EQUIVALENCE 
* (LPAR(~~) I CJ. I (LPAR(~O) , ~1 I (LPAR(Z~) I ~2 1 1 
* (LPAR(22), R2 ), (LPAR(23), GM1 ), (LPAR(24), -a2 ) , 
* (LPAR(25), IMH ), (LPAR(26), IML ), (LPAR(27), IB1 ), 
* (LPAR(28), IB2 ), (LPAR(29), VOMH ), (LPAR(30), VOML ), 
* (LPAR(31) t VM ) 
EQUIVALENCE (ERMSG(l), ERMSGl(1)) 
C 
DATA ERMSG/'UDSAP: I','ER = # F','OR SAMPL1,'E POINT I,'########'/ 
* ,CNIER/11~t12~,~3~,~4'/ 
* tCNSA/'SWI','SPV1't'SPV211'SPvR'/ 
* ,TWOP1/6.283185307179586DO/ 
C 
C+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 
C 
- 
C...TRANSFER WATAND PAWLMETERS INTO LOCAL STORAGE 
DO 10 J=1,31 
10 LPAR(J)=PAR(J) 
C 
C...CHECK TO SEE IF IT IS INITIAL CALL 
IF(ICODE.EQ.2) GOT0 200 
C 
C+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 
C. ..ICODE=l 
C...INITIALIZE CONSTANT 
IERR=O 
C 
C. ..CHECK SUPPLY VOLTAGES 
IF (VPOS . GT . VNEG) GOT0 2 0 
CALL USRMSG ( 'VPOS <= VNEG ' ,12,8) 
IERR=1 
C 
C...CHECK PARAMETER VOLIMH 
20 IF(VOLIMH.GE.(VNEG-VPOS)/2DO.AND.VOLIMH..ODO GOT0 30 
CALL USRMSG ( 'VOLIMH > 0- OR < (VNEG-VPOS) /2 ' ,29; 8) 
IERR=l 
C 
C...CHECK PARAMETER VOLIML 
30 IF(VOLIML.LE.(VPOS-VNEG)/2DO.AND.VOLIML.GE.ODO) GOT0 50 
CALL USRMSG('VOL1ML < 0 OR > 
(VPOS-VNEG)/2',29,8) 
IERR=l 
C 
C...CHECK PARAMETER ISC 
50 IF(ISC.GE.OD0) GOT0 60 
CALL USRMSG('1SC < 01,7,8) 
IERR=l 
C 
C . . . CHECK PARAMETER F1 
60 IF(F1.GT.ODO) GOT0 70 
CALL USRMSG('F1 <= Ot,7,8) 
IERR=l 
C 
C...CHECK PARAMETER F2 
70 PF(F2.GT.ODO) GOT0 80 
CALL USRMSG('F2 <= .01,7,8) 
IERR=l 
C 
C...CHECK ERROR FLAG 
80 IF(IERR.NE.0) GOT0 140 
C 
C...OUTPUT CURRENT SWING 
IMH= (VPOS+VOLIMH) /RO 
IML=-IMH*SRN/SRP 
C 
C...DOMINANT POLE STAGE 
CZ=IMH/SRP 
R2=lDO/(TWOPI*Fl*C2) 
GM2=AO/R2 
C 
C. ..SECOND POLE STAGE 
R1=1D2 
Cl=lDO/ (TWOPI*F2*Rl) 
GMl=lDO/Rl 
C 
C. . . SET INPUT BIAS CURRENT 
IBl=IB+IOS/2DO 
IB2=IB-IOS/2DO 
C 
C...SET VOLTAGE LEVEL FOR INPUT STAGE 
VM= (VPOS+VNEG) /2D0 
C 
C...SET OUTPUT VOLTAGE SWING 
VOMH=VM+ (VPOS-VNEG) / 2 DO+VOLIMH 
VOMLFVM-(VPOS-VNEG)/2DO+VOLIML 
C 
C...CHECX AUTO SAMPLE POINT FLAG 
IF (AUTOSP.NE. 1DO) GOT0 150 
C 
C...SET SPVI SAMPLE POINT 
IVAR= 1 
SA (1) =-lDO+IML/GM2 
INC (1) =ID0 
SA(Z)=SA(l)+lDO 
SA(3)=SA(2)/1Dl 
INC(2)=SA(3) -SA(2) 
INC(3)=-SA(3) 
SA (4 ) =OD0 
INC ( 4 ) =IMH/GM2/1D1 
SA(5) =INC(4) 
INC (5) =INC (4) *9DO 
SA(6)=INC(4) *ID1 
INC ( 6) =ID0 
SA(7)=lDO+SA(6) 
DE=ODO 
LE=5DO 
HE=5DO 
NSA=7 
GOT0 120 
C 
C...SET SPVl SAMPLE POINT 
90 IVAR=2 
GOT0 120 
C 
C...SET SPV2 SAMPLE POINT 
100 IVAR=3 . 
SA(1) =VNEG 
INC ( 1) =VOML-VNEG 
SA ( 2 ) =VOML 
SA(3) = (3DO*VOML+VOMH) /4DO 
INC(2)=SA(3) -SA(2) 
SA(4)=VM 
INC(3)=SA(4) -SA(3) 
SA (5) = (VOML+3DO*VOMH)/4DO 
INC(4)=SA(5) -SA(4) 
SA(6) =VOMH 
INC(S)=SA(6) -SA(5) 
INC ( 6 ) =VPOS -VOMH 
SA ( 7 ) =VPOS 
DE=ODO 
LEISDO 
HE=5DO 
NSA=7 
GOT0 120 
C 
C...SET SPVR SAMPLE POINT 
110 IVAR=4 
SA (1)~-ISC*RO-ID-1 
INC(l)=lD-1 
SA(Z)=SA(l) +1D-1 
INC (2)~-SA(2) 
SA(3) =OD0 
INC(3)=INC(2) 
SA(4)=INC(2) 
INC (4)=1D-1 
SA(5)=INC(2) +ID-1 
DE=ODO 
LE=5DO 
HE=5DO 
NSA=5 
C...CALL UDSAP, IF ERROR, SEND ERROR MESSAGE AND RETURN 
120 CALL UDSAP(MIDA,DERIV,IVARIDEILEIHE,SA,INC,NSAIIER) 
IF(IER.EQ.0) GOT0 (90,100,110,130),IVAR 
ERMSGl(l4)=CNIER(IER) 
ERMSG (5) =CNSA (IVAR) 
CALL USRMSG(ERMSG,36,8) 
C 
C...SET ERROR FLAG 
IERR=l 
GOT0 (90,100,110),IVAR 
C 
C...CHECK ERROR FLAG, IF =I, FLAG WATAND TO TERMINATE THE OPERATION 
130 IF(IERR.NE.1) GOT0 150 
140 VAL(1) =ID0 
GOT0 999 
C 
C...TRANSFER INTERNAL PARAMETERS BACK TO WATAND 
150 DO 160 1=19,31 
160 PAR(1) =LPAR(I) 
GOT0 999 
C 
........................................................................ 
C...ICODE=2 
C...EVALUATE FUNCTION VALUES 
C 
C...GET VARIABLES 
200 VI=VAR(l) 
Vl=VAR (2) 
V2=VAR(3) 
vR=vAR (4) 
C 
C...CURFSNT IN THE SECOND POLE STAGE 
Il=GMl*VI 
C 
C...FIRST POLE STAGE GAIN AND SLEW RATE LIMIT 
12-GM2 *V1 
IF(I2 .LT. IML) I2=IML 
IF(I2 .GT. IMH) I2=IMH 
C 
C...LIMIT CURRENT IN THE FIRST POLE STAGE 
ID=ODO 
IF(V2.GT.VOMH) ID=DEXP(V2-V0MH)-1DO 
IF(V2.LT.VOML) ID=-(DEXP(V0ML-V2)-1DO) 
12-12-ID 
C 
C...SET OUTPUT VOLTAGE LIMITING 
VbV2 
IF (VL. GT . VOMH) VbVOMH 
IF(VL.LT.VOML) VLTVOML 
C 
C...SET OUTPUT CURRENT LIMITING 
IO=vR/RO- 
ILTODO 
IF(IO.GT.ISC) ILTIO-ISC 
IF(IO.LT.-ISC) ILrIO+ISC 
C 
C...ASSIGN FUNCTION VALUES AND RETURN 
VAL ( 1) =VOS 
VAL(2) =IB1 
VAL (3) =IB2 
VAL(4) =VM 
VAL(5) =I1 
VAL(6) =I2 
VAL(7) =VL - 
VAL(8) =IL 
999 RETURN 
Table 4-6 Q source Method Fortran Subroutine 
OA2 FORTRAN: 
c*********************************************************************** 
SUBROUTINE OA2 (ICODE,PAR,VAR,VAL,EPARfMIDAIDERIV) 
c*********************************************************************** 
C 
C OPERATIONAL AMPLIFIER (USING Q SOURCE METHOD) 
C 
C CREATED 17-OCT-87 B.R. HSU EE DEPT. YSU 
........................................................................ 
* 1B1,1B2,VMH,VML,V0MH,V0ML,VM,R1,LPAR(26), 
* VI,V1,V2,VR,QA,QB,IQfVLIILfIOfDEXPITWOPI 
INTEGER ICODE,MIDA(lI ,IVAR,NSA,IER,IERR 
EQUIVALENCE 
* ( LPAR 
* ( LPAR 
.(1), VPOS ), (LPAR(2)lVNEG )t (LPAR( 3)tAO 11 
.1 41, RI I, (LPAR( 51, CI r (LPAR( 6) , RO 1, 
* ~LPAR~ 7j; SRP j; (LPAR~ 81, SRN 1, (LPAR( 91, FI 1, 
* (LPAR(10), F2 ), (LPAR(ll), VOS ), (LPAR(12), IOS ) , 
* (LPAR(13), IB ), (LPAR(14), RIC ), (LPAR(15), ISC ) , 
* (LPAR(16),VOLIMH ), (LPAR(17),VOLIML ), (LPAR(18), AUTOSP) 
EQUIVALENCE 
* (LPAR(19), VMH ), (LPAR(2O), VML ), (LPAR(21), IB1 ) , 
* (LPAR(22), IB2 ), (LPAR(23), VOMH ), (LPAR(24), VOML ), 
* (LPAR(25), VM ), (LPAR(26), R1 ) 
EQUIVALENCE 
* (ERMSG(1) , ERMSGl(1) ) 
C 
DATA ERMSG/'UDSAP: I1,'ER = # Ft,'OR SAMPL1,'E POINT ','########I/' 
* ,CNIER/'lt, '2', '3', '4'/ 
f ,CNSA/'SPVI','SPV1'f1SPV2tf 'SPVR1/ 
* ,TWOP1/6.283185307179586DO/ 
C 
c+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++- 
C 
C...TRANSFER WATAND PARAMETERS INTO LOCAL STORAGE 
DO 10 J=1,26 
10 LPAR(J) =PAR(J) 
C 
C. . . CHECK ICODE 
IF(ICODE.EQ.2) GOT0 200 
C 
- 
........................................................................ 
C...ICODE=l 
C. .INITIALIZE CONSTANT 
IERR=O 
Rl=lDO 
C 
C...CHECK SUPPLY VOLTAGES 
IF(VPOS.GT.VNEG) GOT0 20 
CALL USRMSG('VSUP.1 <= VSUP.2',16,8) 
IERR=l 
C 
C...CHECK PARAMETER VOLIMH 
20 IF (VOLIMH. GE. -VPOS .AND. VOLIMH. LEE ODO) GOT0 25 
CALL USRMSG('VOLIM.1 > 0 OR < -VSUP.1',24,8) 
IERR= 1 
C 
C...CHECX PARAMETER VOLIML 
25 IF(VOL1ML.U.-VNEG.OR.VOLIML.GE.OD0) GOT0 30 
CALL USRMSG('VOLIM.2 < 0 OR > -VSUP.2',24,8) 
L 
C...CHECX PARAMETER ISC 
30 IF(ISC.GE.OD0) GOT0 40 
CALL USRMSG('1SC < 0',7,8) 
L 
C...CHECX PARAMETER F1 
40 IF(F1.GT.ODO) GOT0 45 
C 
C...CHECK PARAMETER F2 
45 IF(F2.GT.ODO) GOT0 50 
L 
C...CHECX ERROR FLAG 
50 IF(IERR.EQ.1) GOT0 120 
L 
C...SET INPUT BIAS CURRENT 
IBl=IB+IOS/2DO 
IB2=IB-IOS/2DO 
C 
C...CALCULATE MAXIMUM INPUT VOLTAGE FOR SLEW RATE LIMITING 
VMH=SRP/ (TWOPI*Fl*AO ) 
VML=-SRN/ (TWOPI*Fl*AO ) 
C 
C...SET VOLTAGE LEVEL FOR INPUT STAGE 
VM= (VPOS+VNEG) /2DO 
C 
C. ..COMPUTE MAXIMUM OUTPUT VOLTAGE 
VOMH=VM+(VPOS-VNEG)/2DO+VOLIMH 
VOML=VM- (VPOS -VNEG) / 2 DO+VOLIML 
C 
C...CHECX AUTO SAMPLE POINT FLAG 
IF (AUTOSP. NE. 1DO) GOT0 13 0 
C 
C...SET SPVI SAMPLE POINT 
IVAR= 1 
SA(1) =-lDO+VML 
SA(2) =VML-1D-3 
INC (1) =999D-3 
SA(3) =VML 
INC (2) =1D-3 
SA(4) =VMH 
INC ( 3 ) =VMH-VML 
SA (5) =P+lD-3 
INC (4) =ID-3 
SA(6) =lDO+VMH 
INC (5) ~999D-3 
DE=ODO 
LE=5DO 
HE=5DO 
NSAr6 
GOT0 100 
C 
C...SET SPVl SAMPLE POINT 
6 0 IVAR=2 
SA ( 1) =-1D5 
INC (1) -99D3 
SA(2) =-1D3 
INC ( 2 ) =1D3 
SA(3) =OD0 
INC 3 1 =lD3 
C 
C...SET SPV2 SAMPLE POINT 
7 0 IVAR=3 
SA ( 1) =VNEG 
SA ( 2 ) =VOML 
INC(l)=SA(2) -SA(l) 
SA(3) =(3DO*VOML+VOMK)/4DO 
INC(2)=SA(3) -SA(2) 
SA(4) =VM 
INC(3)=SA(4) -SA(3) 
SA(5) =(VOML+3DO*VOMH)/4DO 
INC(4) =SA(5) -SA(4) 
SA ( 6 ) =VOMH 
INC(5)=SA(6) -SA(5) 
SA ( 7 ) =VPOS 
INC(6) =SA(7) -SA(6) 
DE-OD0 
LE=lDl 
HE-1D1 
NSA-7 
GOT0 100 
C 
C...SET SPVR SAMPLE POINT 
8 0 IVAR-4 
SA (1) =-ISC*RO-1D-3 
INC (1) =ID-3 
SA (2) =-ISC*RO 
INC(2) =-SA(2) 
SA(3) =OD0 
INC(3)=INC(2) 
SA(4) =INC(2) 
INC (4) =ID-3 
SA(5)=INC(2) +ID-3 
DE-OD0 
LE-5DO 
HE=5DO 
NSA=5 
C 
C...CALL UDSAP, IF ERROR, SEND ERROR MESSAGE AND RETURN 
100 CALL UDSAP(MIDA,DERIV,IVAR,DE,LE,HE,SA,INC,NSA,IER) 
IF(IER.EQ.0) GOT0 (60,70,80,110) ,IVAR 
ERMSGl(l4) =CNIER (IER) 
ERMSG ( 5 ) =CNSA ( IVAR) 
CALL USRMSG(ERMSG,36,8) 
C 
C...SET ERROR FLAG 
IERR=l 
GOT0 (60,70,80),IVAR 
C 
C. ..CHECK ERROR FLAG, IF = 1, FLAG WATAND TO TERMINATE THE OPERATION 
110 IF(IERR.NE.1) GOT0 130 
120 VAL(1) =1DO 
GOT0 999 
C 
C...TRANSFER INTERNAL PARAMETERS BACK TO WATAND 
130 DO 140 I=19,26 
140 PAR(I)=LPAR(I) 
GOT0 999 
C 
........................................................................ 
C. ..ICODE=2 (EVALUATE FUNCTION VALUES) 
C . . . GET VARIABLES 
200 VI=VAR(l) 
Vl=VAR ( 2 ) 
V2=VAR(3) 
VR=vAR ( 4 ) 
C 
C...LIMIT INPUT VOLTAGE CHANGE FOR SLEW RATE FUNCTION 
IF (VI . GT . VMH) VI=VMH 
IF (VI . LT. VML) VI=VML 
C 
C...TWO-POLE GAIN FUNCTIONAND VOLTAGE LIMITING 
QA=V2 
QB=VL/(Fl*F2*TWOPI**2) 
IQ=AO*VI-(F1+F2)*V1/(F1*F2*TWOPI) 
IF (V2. LT .VOML) IQ=IQ+ (DEXP (VOML-V2) -1DO) 
IF (V2. GT. VOMH) IQ=IQ- (DEXP (V2-VOMH) -lDO ) 
C 
C...SET OUTPUT VOLTAGE SWING 
VGV2 
IF (VL . GT . VOMH) VPVOMH 
IF (VL . LT . VOML) VL'VOML 
C 
C...SET MAXIMUM OUTPUT CURRENT 
IO=VR/RO 
IL=ODO 
IF(IO.GT.ISC) 1-10-ISC 
IF (10. LT. -1SC) IL=IO+ISC 
C 
C...ASSIGN FUNCTION VALUES AND RETURN 
VAL ( 1 ) =VOS 
VAL(2) =IB1 
VAL (3 ) -1B2 
VAL(4) =VM 
VAL ( 5 ) =QA 
VAL(6) =QB 
VAL(7) =IQ 
VAL(8) =VL 
VAL(9)=IL - 
999 RETURN 
END 
CHAPTER V 
MACROMODEL PERFORMANCE 
To investigate the validity of the macromodel, five 
illustrative examples are presented in this chapter. These 
examples cover a wide range of applications. The RC circuit 
model with the default 741 op amp parameters is used for 
these simulations. 741C op amps are used for the laboratory 
tests. The results of computer simulations are compared 
with experiments, and an execution time comparison between 
the RC circuit and the Q source models is presented in 
section 5.6. All examples are run using WATAND version 
1.10-00. 
5.1 INVERTING AMPLIFIER 
The inverting amplifier circuit of Fig. 5-1 provides 
tests with respect to voltage gain versus frequency and 
voltage limits. The simulation output is compared with the 
experiments and is shown in Figs. 5-2 to 5-4. Fig. 5-2 is 
the frequency domain analysis of the voltage gain. The 
transient responses of sinewave inputs with peak value 0.3 V 
is shown in Fig. 5-3 and with peak value of 10 V is shown in 
Fig. 5-4. The results show good agreement with the values 
found experimentally. The offset characteristics are also 
tested for this circuit and are shown in Table 5-1. The 
- 
first DC analysis shown there is with zero offset current 
and voltage. The second analysis has offset voltage of 
2 mV. The last DC analysis is with bias current of 80 nA 
and offset current 20 nA. These results show that the offset 
voltage causes more DC shift than the bias and offset 
currents do, for this circuit. 
IAMP WATAND: 
#T AN INVERTING AMPLIFIER 
#M 
OA. 1 
#D 
V.S 10 SIN .3 1K 0 
R.l 1 2 100 
R.P 3 0 100 
R.F245K - 
R.L 4 0 10K 
OA.l.l 3 2 4 0 
#E 
#GV GAIN ( V 4 / V 1 ) 
#GI V.S V 1 
DC PR OU ALL 
TC PS V.S NPER 2 OU V 4 G VIN VB -15 15 IB -.5 .5 PL 
FR BE 100 EN lOME LO 10 DB PP OU G GAIN VB -10 40 KE ALL ON D 
#S - 
Fig. 5-1 An Inverting Amplifier Circuit and its WATAND 
Netlist. 
FR Vt ,19-0G SR137015 14.0CT-87 16:45:34 YSUCMS FILE: lAMP 
XT AN INVERTING AMPLIFIER 
V 
40 1 
EXPERIMENTAL 
2 0 
FR EXECUTION TIME: 0,227 SECI 
Fig. 5-2 WATAND and Experimental Voltage Gain Versus 
Frequency. 
TC VI ~10.96 SRt37015 t4.OCT.8? 16141:?8 YSUCMS FILE: IAMP 
tt AN INVERTING AMPLIFIER 
I V 
TC EXECUTION TIME: 0 1543 SECa 
Fig. 5-3 Voltage Limiting Effect with V.S = 0.3 V Amplitude. 
Table 5-1 DC Solutions of the Inverting Amplifier. 
DC V1.lO-0g SR137015 15-OCT-87 21:41:20 YSUCMS FILE: IAMP 
............................ 
SOL'N # 1 (DET -) 0 ITER. 
............................ 
( 1) 0.0 ( 2) -1.66542D-18 ( 3) -8.32667D-23 
( 4) -8.49405D-17 ( 
I V. S -1.66542D-20 A1 OA. 1 -1.66542D-18 
A2 OA. 1 0.0 A3 OA. 1 9.87708D-19 
A4 OA.l -8.68266D-17 A5 OA. 1 -8.68266D-17 
A6 OA.l -8.32667D-25 A7 OA. 1 -8.32750D-28 
A8 OA. 1 2.51491D-20 
DC EXECUTION TIME- 0.003 SEC. 
$am oa. 1 vos 2m 
ALTER PERFORMED 
dc 
DC V1.lO-0g SR137015 15-OCT-87 21:41:36 YSUCMS FILE: IAMP 
............................ 
SOL'N # 1 (DET -) 5 ITER. 
............................ 
( 1) 0.0 ( 2) 1.99948D-03 ( 3) -2.60595D-11 
( 4) 1.01973D-01 ( 
I V.S 1.99948D-05 A1 OA. 1 -5.21215D-07 
A2 OA. 1 0.0 A3 OA.l 5.21189D-07 
A4 OA.l 1.04238D-01 A5 OA.l 1.04238D-01 
A6 OA.l -2.60595D-13 A7 OA. 1 9.99739D-13 
A8 OA. 1 -3.019210-05 
- 
DC EXECUTION TIME= 0.023 SEC. 
+am oa.1 vos 0 ib 80n ios 20n 
ALTER PERFORMED 
dc 
DC V1.lO-0g SR137015 15-OCT-87 21:41:55 YSUCMS FILE: IAMP 
............................ 
SOL'N # 1 (DET -) 4 ITER. 
............................ 
( 1) 0.0 ( 2) -8.99944D-06 ( 3) -9.00000D-06 
( 4) -1.08972D-04 ( 
I V.S -8.99944D-08 A1 OA. 1 -8.99944D-06 
A2 OA.l 0.0 A3 OA. 1 -5.56442D-10 
A4 OA. 1 -1.11288D-04 A5 OA.l -1.11288D-04 
A6 OA.l 2.78221D-16 A7 OA.l 1.60000D-07 
A8 OA. 1 3.08916D-08 
- 
DC EXECUTION TIME= 0.027 SEC. 
V1 ,10-06 SR137015 08-OCT.87 17:03: 17 YSUCtlS FILE: IAMP 
AN INVERTI~~I~I AIIPLIFIER 
TC EXECUTION TIME: 0,633 SEC I 
Fig. 5-4 Voltage Limiting Effect with V.S = 10 V Amplitude. 
5.2 MONOSTABLE MULTIVIBRATOR 
To estimate the slew rate characteristics and output 
voltage limits of the op amp model, the monostable - 
multivibrator circuit [18] shown in Fig. 5-5 is simulated. 
The DT analysis (DT SN 4 3 SO -lM 1M ZS) shows three DC 
solutions in this circuit (see Table 5-2). The last DC 
- - 
solution is the desired initial point for TC analysis. Fig. 
5-6 is the simulation output and the experimental result. 
The slopes from point A to B and C to D show the slew rate 
limiting. A sharper sloped pulse can be generated by using 
a faster slew-rate op amp such as the LF355. It is seen - 
that the simulation and experimental output are in good 
agreement. 
MONS WATAND: 
#T A MONOSTABLE MULTIVIBRATOR 
#M 
OA. 1 
D1.l 
#D - 
v.s 1 0 PW 0 0 20MU 0 20.001MU -5 100MU -5 100.001MU 0 
R.P 2 0 10K 
R.F 4 5 10K 
R.l 5 3 10K 
R.2 3 0 1K 
R.3 6 5 1K 
C.l 1 2 .1MU - 
C.2 4 0 .1MU 
D1.l.l 4 0 
D1.1.2 3 2 
D1.1.3 6 4 
OA.l.l 3 4 5 0 
#E 
DT SN 4 3 SO -lM 1M ZS OU ALL PR 
TC IP DT OU V 5 V 1 EN .4M DE 1MU VB -15 15 PL 
#S - 
Fig. 5-5 A Monostable Multivibrator Circuit and its WATAND 
Netlist. 
Table 5-2 The DC Solutions of the Monostable Multivibrator. 
dt 
DT V1.10-OgSR137015 17-OCT-87 12:53:25 YSUCMS FILE:MONS 
............................ 
SOL'N $ 1 (DET -) 19 ITER. 
............................ 
( 1) 0.0 ( 2) -8.41750D-13 ( 3) 
( 4) -1.24779D-08 ( 5) 7.99907D-04 ( 6) 
I V.S 0.0 A1 Dl. 1 
A1 D1.2 -8.41834D-13 A1 Dl. 3 
A1 OA. 1 -1.24779D-08 A2 OA. 1 
A3 OA. 1 4.05953D-09 A4 OA.l 
A5 OA. 1 8.11907D-04 A6 OA.l 
A7 OA. 1 1.60000D-07 A8 OA.l 
............................ 
SOL'N # 2 (DET +) 38 ITER. 
............................ 
A1 D1.2 
A1 OA.l 
A3 OA. 1 
A5 OA. 1 
A7 OA. 1 
SOL'N # 3 (DET -) 52 ITER. 
............................ 
( 1) 0.0 ( 2) 4.85614D-01 ( 3) 
( 4) 7.55084D-01 ( 5) 1.25016D+01 ( 6) 
I V.S 0.0 A1 Dl. 1 
A1 D1.2 4.85663D-01 A1 D1.3 
A1 OA. 1 7.55084D-01 A2 OA.l 
A3 OA.l 3.37049D-01 A4 OA.l 
A5 OA. 1 1.35000D+01 A6 OA.l 
A7 OA.l 1.60924D-07 A8 OA.l 
DT EXECUTION TIME= 0.273 SEC. 
TC Vi 118-86 SR137015 14.OCT.87 i6134:39 YSUCHS FILE: HONS 
IT A RONOSTABLE IULTIVIBRATOR 
v 
15 
10 
5 
0 
-5 
EXPERIMENTAL 
TC EXECUTION TINE: 8 1873 SEC I 
Fig. 5-6 The Input/Output Voltages of the Monostable 
Multivibrator. 
5.3 SINGLE POWER SUPPLY NON-INVERTING AMPLIFIER 
- 
A non-inverting amplifier circuit using a single 
power supply [12] is shown in Fig. 5-7. The gain of this 
amplifier is 11. Fig. 5-8 is the output of the amplifier. 
+ 
VVo is the output voltage with a average value of V--/2. The 
bandwidth of this amplifier is shown in Fig. 5-9. The low 
frequency cutoff, fl, and high frequency cutoff, fh, from 
WATAND simulation are 50 Hz and 84k Hz. The experimental 
results for fl and fh are 50 Hz and 85k Hz. The results of 
- 
the WATAND simulation and the experiment are very close. 
SPS WATAND: 
#T A NON-INVERTING AMPLIFIER WITH SINGLE SUPPLY 
#M 
OA.l VSUP 15 0 FB 4.5 
#D 
V.S 1 0 SIN .4 1K 0 
V.CC 5 0 DC 15 
R.F 4 3 50K 
R.l 5 2 106.7K 
R.2 2 0 106.7K 
R.3 3 7 5K 
R.1 6 1 50 
C.l 7 0 1.01MU 
C.1 2 6 .101MU 
C.0 4 8 1MU 
R.L 8 0 10K - 
OA.l.l 2 3 4 0 
#E 
#GV GAIN ( V 8 / V 1 ) 
#GI PHASE CALL GAPH ( V 8 / V 1 , -1 ) 
DC PR OU ALL 
TC PS V.S NPER 2 OU V 4 V 8 VB -6 14 PP KE ALL ON D 
FR BE 1 EN lOME LO 10 PP OU G GAIN VB 0 12 KE ALL ON D 
DI US FR ON D OU G PHASE VB 0 360 PP 
#S - 
Fig. 5-7 A Single Power Supply Amplifier Circuit and its 
WATAND Netlist. 
TI V1 ,113-136 5Rl271315 Bi.0CT-87 15:46:55 f51!C115 FILE: SPS 
RT A bIOti-INVERTIbili AC iiHFL1FIER NITH SIllliLE ZUFFLY 
I EXPERIMENTAL 1 
I 
,13010 ,81315 ,813213 
!! . V 4.9 I) . ld 8-13 
VOLTAGE:!' 
TC EXECUTION TIME: 0,239 5EC 0 
Fig. 5-8 Output Waveform of the Single-Supply Amplifier. 
FR Vi 110.06 SR137015 07.OCT.$7 1F:3?122 YSUCMS FILE: SPS 
DT A NON-INVERTING AC AMPLIFIER WITH jIN6LE SUPPLY 
12 
+- 
EXPERIMENTAL 
./ .--. 
10 - 4 
t 
8 - 
\ 
\ 
b 
', 
6 - 
', 
4 - 
2 - 
0 
lEtf 1Et2 1Et5 1Et 
W - 6V 5AIl,l 
FR EXECUTION TIME: 0,433 SEC, 
Fig. 5-9 Voltage Gain as a Function of Frequency. 
5.4 TRIANGULAR WAVE GENERATOR 
The triangular wave generator circuit shown in Fig. 
5-10 consists of a comparator OAl and an integrator OA2. 
The comparator compares the voltage at point A, VA, contin- 
uously with the inverting input that is at 0 V. When VA 
goes slightly above or below zero, the output of OAl, VB, 
goes to the positive or negative saturation level, respec- 
tively. The integrator converts the square wave input, VB 
to the triangular wave. The Zeners, Dl and D2, at the 
output of OAl are used to limit the amplitude of the square 
wave. The circuit netlist in WATAND shown in Fig. 5-10 uses 
the parameter VOLIM to limit the square wave instead of 
using Zeners. Because the output of OAl, VB, is bistable, a 
command (#IP DC AL VN 1 7) is used to apply a pulse to the 
circuit at zero time which initiates oscillation. The DC 
solution is shown in Fig. 5-11 with node 1 of seven Volts. 
The result of the simulation and the experiment shown in 
- 
Fig. 5-11 again agree well. 
5.5 R-active bandpass filter 
An R-active bandpass filter using two op amps- is 
shown in Fig. 5-12. The simulation results in the small 
signal response are compared with the experiments presented 
in Ref. [8] and both are very similar (see Fig. 5-13). The 
center frequency is lOOk Hz for both simulation and 
experimental result. 
- 
TRI WATAND: 
#T TRIANGULAR GENERATOR (F=500) (#IP DC AL VN 1 7) 
#M 
0A.A VOLIM -7.6 7.6 
OA. B 
#D 
R.l 15 10K 
R.2 3 6 10K 
R.3 3 1 20K 
C.l 5 6 .1MU 
OA.A.1 3 0 1 0 
OA.B.2 0 5 6 -0 
#E 
DC OU ALL PR 
TC OU V 6 V 1 EN 4M DE 20MU VB -8 8 PP 
#S 
Fig. 5-10 A Triangular Wave Generator Circuit and its 
WATAND Netlist. 
#ip dc a1 vn 1 7 
#q tip (dc 
IP NAME: DC 
( 1) 7.00000D+00 ( 3) 3.83209D-09 ( 5) -2.12267D-09 
( 6) 4.21060D-04 ( 
A1 OA. 1 0.0 A2 OA. 1 0.0 
A3 OA. 1 3.83209D-09 A4 OA.l 7.66418D-04 
A5 OA. 1 7.66418D-04 A6 OA.l -1.91604D-15 
A7 OA. 1 1.60000D-07 A8 OA.l -1.13684D-07 
A1 OA. 2 -2.12267D-09 A2 OA. 2 0.0 
A3 OA.2 2.12267D-09 A4 OA.2 4.24534D-04 
A5 OA. 2 4.24534D-04 A6 OA.2 -1.06133D-15 
A7 OA.2 1.60000D-07 A8 OA.2 -4.63162D-08 
EXTRA= 0.0 
TC !'I ,113-95 FC1:!8981 131-1!CT.,3i 17:21122 YSUCHS FILE: TRI 
#T-TRIAH6VLAR GENERATOR (F:SBl3) (#If DC ALT VH i 7) 
TC EXECUTION TINE: i ,lBO 5EC, 
Fig. 5-11 The DC Initial Point and the Output Waveform of 
the Triangular Wave Generator. 
BRF WATAND: 
#T A BANDPASS R-ACTIVE FILTER 
#M 
OA.l FB 5.375 
#D 
V.S 1 0 SIN 3M 1K 0 
R.G 1 2 600 
R.l 4 5 10K 
R.2 5 6 90 
R.3 6 3 100 
R.4 3 0 9.9K 
OA.l.l 2 3 4-0 
OA.1.2 5 6 6 0 
#E 
#GV GAIN ( V 4 / V 1 ) 
DC PR OU ALL 
FR BE 50K EN 200K LI 200 DB PL OU G GAIN VB 15 45 
#S 
- 
Fig. 5-12 An R-Active Bandpass Filter Circuit and its 
WATAND Netlist. 
FR V1 ,18.06 SR137015 14-OCT.87 17:00: 10 YSUCHS 
DT A BANDPASS RmACTIVE FILTER 
FILE: BRF 
I EXPERIMENTAL 
FR EXECUTION TINE: 8 1733 SEC 4 
Fig. 5-13 The Response of an R-Active Bandpass Filter. . 
5.6 MODEL COMPARISON - 
The above computer outputs were simulated by using 
the RC circuit model. Simulations using the Q source model 
were run to compare with the RC circuit model's output. 
- - 
Simulation outputs for both models have only minor differ- 
ences due to sample-point choice, but execution times are 
different. Table 5-1 is the CPU time list for these two 
models when running the above examples. In almost every 
case the RC model is faster than the Q source model, and. - 
especially in FR (frequency domain) analysis. 
Table 5-3 Simulation Time Comparison. 
FILE ANALYSIS SIMULATION TIME (sec) 
Q source RC circuit 
Model Model 
IAMP DC 
FR (Fig. 5-2) 
TC (Fig. 5-3) 
TC (Fig. 5-4) 
MONS 
SPS 
TRI 
BRF 
DC 
TC (Fig. 5-6) 
DC 
TC (Fig. 5-8) 
FR (Fig. 5-9) 
DC 
TC (Fig. 5-11) 
DC 
FR (Fig. 5-13) 
DC ANALYSIS 
SUBTOTAL TC ANALYSIS 
FR ANALYSIS 
TOTAL CPU TIME 13.97 10.087 
CHAPTER VI 
CONCLUSION 
Two macromodels of the operational amplifier have 
been presented. When designing these op amp macromodels, 
the major considerations were to keep the model size small 
(less execution time and memory space) and to model the op 
amp's large-signal response characteristics. 
The macromodel using the RC circuit method has nine 
passive elements, eight dependent sources, and four 
independent variables. The other macromodel using the Q 
source method has seven passive elements, nine dependent 
sources, and four independent variables. The complexity of 
each of these macromodels is almost twice that of the BJT 
transistor models in WATAND. Compared with the real op amp, 
such as the 741 which has twenty four transistors and twelve 
passive elements, the size of these macromodels is small. - 
These macromodels can simulate the most important character- 
istics, such as slew rate limiting, input and output 
characteristics, offset characteristics, voltage gain versus 
- - 
frequency, output voltage limiting, and short-circuit 
current limiting. The trade off for the small size of the 
op amp macromodel is that some less important character- 
istics in circuit analysis are not modeled. These include 
common-mode gain, thermal effects, and power supply 
rejection ratio. 
The Q source model is a bit simpler than the RC 
circuit model but the latter has a faster average simulation 
speed especially in frequency domain analysis. The 
simulation results in Chapter 5 show these models are 
accurate enough and efficient for general large- and small- 
signal circuit analysis. 
REFERENCES 
1. M. Vlach, WATAND User's Manual, revised by P.R. Bryant 
and H.J. Strayer, V1.09. University of Waterloo, Dec. 
1985. 
2. J.A. Barby, A WATAND Study, University of Waterloo, 
Tech. Report No. UW EE 81-05, Sep. 1981. 
3. I.N. Hajj, K. Singhal, J. Vlach, and P.R. Bryant, 
"A Program for the Analysis and Design of Linear and 
Piecewise-Linear Networks," Proc. of 16th Midwest 
Svm~osium on Circuit Theory, Vol. 1, VI.4.1-VI.4.9, 
April 1973. 
4. P.C. Munro, ''Chapter 8 User-Defined Elements, Analyses, 
and Control Words,I1 rewritten for WATAND User's Manual, 
Sep. 1986. 
5. H.J. Strayer, D.J. Roulston, P.R. Bryant, "DC Solution 
Speed in Piecewise Linear Network Analysis Programs," 
Electronics Letters, Vol. 22, No. 3, Jan. 1986, 
pp. 165-166. 
6. G.R. Boyle, B.M. Cohn, D.O. Perderson, and J.E. Solomon, 
 macrom modeling of Integrated Circuit Operational 
Amplifiers,'' IEEE J. Solid-State Circuits, Vol. SC-9, 
Dec. 1974, pp. 353-363. 
7. M. Glesner and C. Weisang, "Computer Aided ~acromodelin~ 
of Integrated Circuit Operational Amplifiers," in IEEE 
Proc. ISCAS/76, 1976, pp. 255-258. 
- 
8. E. Sanchez-Sinencio and M.L. Majewski, "A Nonlinear 
Macromodel of Operational Amplifiers in the Frequency 
Domain," IEEE Transactions on circuit and systems, Vol. 
CAS-26, June 1979, pp. 395-402. 
9. P. Weil and L.P. McNamee, "A Nonlinear Macromodel for 
Operational Amplifiers,~~ Int. J. Circuit Theory- ADD^.^ 
Vol. 6, 1978, pp. 57-64. 
10. T.M. Frederiksen, Intuitive IC OD AmD, R.R. Donnelley & 
Sons, 1984. 
11. S. Soclof, Analoq Inteqrated Circuits, Prentice-Hall 
Inc., 1985. 
12. A. Gayakward, OD-Am~s and Linear Inteqrated Circuit - 
Technoloay, Prentice-Hall, Inc., 1983. 
13. J.E. Solomon, "The Monolithic Op Amp: A Tutorial Study,I1 
IEEE J. Solid-State Circuits, Vol. SC-9, Dec. 1974, 
pp. 314-332. 
14. J. Vlach and K. Singhal, Computer Methods for Circuit 
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15. J. F. Suen, "Computer-Aided Design: Monte-Carlo DC 
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16. J. Lin and J.H. Nevin, ''A Modified Time-Domain Model 
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IEEE J. Solid-State Circuits, Vol. Sc-21, June 1986, 
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17. P.C. Munro, "Chapter 9 Imbed and Macro Fa~ilities,~~ 
rewritten for WATAND User's Manual, April 1987. 
18. R.F. Coughlin and F.F. Driscoll, Operational Amplifiers 
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