Adapting the Skyline Operator in the NetFPGA Platform

Abstract

Attacks directed at networks and end systems are continually on the rise. The issue has been gathering much attention as of late. In his 2013 State of the Union Address, the President of the United States addressed the severity of the issue in regards to national security. Systems which can detect and prevent attacks are an essential component in keeping our communication infrastructure safe. Many software solutions are publicly available, but are unable to meet the demands of a high rate networks. These environments require platforms which provide open source hardware accelerators designed for the Internet Protocol. The goal of this study is to determine the complexity of adapting the Skyline algorithm -- a well-known algorithm used in databases -- to the NetFPGA hardware accelerated platform. Additionally, one possible application of Skyline could be detecting the presence of malicious packets under the assumption that criteria for malicious packet detection are given prior Skyline computation. The contribution of this work is twofold. Firstly, we propose a novel representation of the Skyline BNL algorithm using a state machine for two dimension multi-criteria consisting of the packet length and number of reoccurring IP addresses. Our goal is to create an implementation to help determine design considerations for translating Skyline to the NetFPGA. Finally, we develop an implementation of Skyline using the hardware description language Verilog. The evaluation of this implementation was performed using Icarus Verilog. The results indicate our prototype can accurately compute the Skyline of network communications across two dimensions.