Digital.Maag Repository

An 8 bit serial communication module chip design using synopsys tools and ASIC design flow methodology

Show simple item record

dc.contributor.author Munugala, Anvesh
dc.date.accessioned 2018-10-29T20:32:39Z
dc.date.accessioned 2019-09-08T02:28:22Z
dc.date.available 2018-10-29T20:32:39Z
dc.date.available 2019-09-08T02:28:22Z
dc.date.issued 2018
dc.identifier.other .b22420265
dc.identifier.uri http://hdl.handle.net/1989/13044
dc.language.iso en_US en_US
dc.title An 8 bit serial communication module chip design using synopsys tools and ASIC design flow methodology en_US
dc.type Thesis en_US


Files in this item

This item appears in the following Collection(s)

Show simple item record

Search Digital.Maag


Advanced Search

Browse

My Account